The present invention relates to burn-in technology for integrated circuits and in particular to burn-in technologies for unpackaged integrated circuits for use in Multichip Modules.
A certain percentage of the integrated circuits (ICs) formed in a manufacturing process fail in the first hours or days of use. The infant mortality of the ICs results from latent defects in the device as manufactured. Semiconductor circuits having a relatively large die size and relatively thin gate oxides are particularly susceptible to infant mortality.
The bulk of early failures may be detected by applying power and then supplying a series of test signals to the circuit thereby extensively exercising the circuits at high temperature. Devices which do not respond properly to the test signals or otherwise fail can then be discarded before shipment. This test procedure is called burn-in.
In a typical burn-in process, a large number of packaged ICs are individually mounted on printed circuit boards having a circuit design that permits the ICs to be exercised in parallel. The printed circuit board loaded with ICs is then placed in a burn-in oven. The burn-in oven controls the ambient temperature during the test process. Generally, ICs are burned in for 72 hours or more at temperatures exceeding 100.degree. C.
The burn-in process imposes many significant cost penalties on chip manufacturers. For example, the physical space required to mount individual packaged chips on a few printed circuit boards can consume several cubic feet. The facility space necessary to burn-in a significant number of test assemblies of this size can therefore easily occupy a city block. Furthermore, the power required to heat the burn-in oven and power the ICs is considerable. Assembly of the ICs into sockets onto printed circuit boards is also labor intensive and may damage ICs which might otherwise survive the burn-in process.
In addition to cost penalties, the conventional burn-in process is performance limited. The long lead lines of printed circuit boards and other conventional packaging can create electrical noise and limit the overall operating speed of the circuit to a few MHz. So long as the ICs being tested do not operate faster than the performance of the test circuit board or, alternately if the IC is ultimately to be packaged on a board having similar performance characteristics, the performance limitations of the burn-in test package are of minimal concern.
Modern ICs, however, are capable of operating in excess of 40 MHz. Therefore, multichip modules (MCMs) are emerging as the packaging and interconnection medium of choice for high performance and on high density electronics systems, both commercial and military. FIG. 1 is a cross-sectional view of one type of MCM. The MCM contains a base high density interconnect substrate (HDI) 40 over which is located conducting power and ground planes 42 and 44. Power and ground planes 42 and 44 are in turn separated from each other by insulating layer 48. Contact to the power and ground planes may be directly made using vias (not shown). Positioned above the power and ground planes is a second dielectric layer 70 which insulates the power and ground planes 42 and 44 from metal interconnect layers 76 and 77. A plurality of ICs 90 attach to the surface of the HDI to form the MCM. ICs 90 contact interconnect layers 76 and 77 through vias 79. The surface of the typical MCM may contain a passivation layer 86. There are a variety of technologies which may be used to implement each of these elements and as stated above, the structure of FIG. 1 is but one example of an MCM structure. A system assembled using MCMs permits system operation at the faster operating speeds of modern ICs in addition to providing cost, size, weight, and reliability advantages over conventional packaging.
Two generic problems of great concern to current and prospective manufacturers of MCMs are test-at-speed and burn-in of the chips. If chips cannot be verified as functional under the desired operating speeds, assembling the chips into an MCM may not gain the desired performance advantages. Even if the chips can be assembled on an MCM and then tested at speed, removal and replacement of embedded chips exacerbates the difficulties of fault isolation, adds significant cost and yield risk to the module, and incurs the need for sophisticated tracking and handling capabilities. Furthermore, the reworked part cannot, in general, be of equal quality to the virgin part.
Even if chips can be satisfactorily pre-tested at speed, chip burn-in losses hinder the ability to manufacture MCMs with reasonable yields. Burn-in losses can be as high as 5% per chip for complex logic chips (e.g., state-of-the-art microprocessors), and are seldom much less than 1% per chip. For example, a 20-chip module in which all the chips have a 5% burn-in failure probability has only a 36% probability of surviving burn-in.
One proposed solution to burn-in losses is to use tape-automated bonding (TAB) technology to burn in the chips on tape prior to module assembly. The tape, however, can warp during extended high-temperature (125.degree.-150.degree. C.) operation, due to different stress relaxation processes in the various metal, adhesive, and polyimide layers of the tape/chip combination. This approach therefore does not satisfy many of the desired burn-in test apparatus criteria.
Manufacturers of MCMs therefore need a reliable method and device for testing individual ICs and conducting burn-in tests prior to assembling the chips onto an MCM. In particular, to minimize handling damage and cost of fixturing, the method and device can ideally be implemented on a wafer scale. In this manner, manufacturers could use a single, instead of multiple, fixturing device.